Display device

ABSTRACT

A display device includes a first substrate, a plurality of pixels on the first substrate, a first light shielding layer on the first substrate, a second substrate, and a second light shielding layer on the second substrate. The first light shielding layer extends in the first direction, the second light shielding layer extends in a second direction intersecting the first direction, and apertures of the plurality of pixels are defined by the first light shielding layer and the second light shielding layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/716,342, filed on Apr. 8, 2022, which application is based upon andclaims the benefit of priority from the prior Japanese PatentApplication No. 2021-066721, filed on Apr. 9, 2021, the entire contentsof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

An embodiment of the present invention relates to the structure ofpixels of a display device.

Description of Related Art

The liquid crystal panel is arranged with a light shielding film so thatlight incident from the outside does not affect the operation of aswitching element (thin film transistor) by repeating multiplereflections inside. The structure and arrangement of the light shieldingfilm arranged on the display panel are various. For example, JapanesePatent Laid-Open No. H10-206889 discloses a display device in which alight shielding film arranged on a substrate on which a switchingelement is formed, and a black matrix arranged on a counter substrateare formed of a metal film and a blackened transparent conductive film.

SUMMARY OF THE INVENTION

A display device in an embodiment according to the present inventionincludes a first substrate, a plurality of pixels on the firstsubstrate, a first light shielding layer on the first substrate, asecond substrate, and a second light shielding layer on the secondsubstrate. The first light shielding layer extends in a first direction,the second light shielding layer extends in a second directionintersecting the first direction, and apertures of the plurality ofpixels are defined by the first light shielding layer and the secondlight shielding layer.

An array substrate in an embodiment according to the present inventionincludes a first substrate, a plurality of pixels on the firstsubstrate, a first light shielding layer arranged on the first substrateand extending in a first direction, a plurality of data signal linesextending in a second direction intersecting the first direction andintersecting the first light shielding layer, a pixel electrode arrangedin each of the plurality of pixels, a common electrode overlapping thepixel electrode, and a common auxiliary electrode having a lightshielding property and laminated on the common electrode. Each apertureof the plurality of pixels is defined by the first light shielding layerand the common auxiliary electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of the first substrate side of adisplay device according to an embodiment of the invention;

FIG. 2 is a cross-sectional view of a pixel of a display deviceaccording to an embodiment of the invention;

FIG. 3 is a plan view of the pixel part of a display device according toan embodiment of the invention;

FIG. 4 is a plan view of the first sub-pixel, second sub-pixel, andthird sub-pixel of a display device according to an embodiment of theinvention;

FIG. 5 is a plan view of a pixel part of a display device according toan embodiment of the invention;

FIG. 6 is a plan view showing a configuration of a first light shieldinglayer arranged in a pixel part of a display device according to anembodiment of the present invention;

FIG. 7 is a plan view showing a configuration of a semiconductor layerarranged in a pixel part of a display device according to an embodimentof the present invention;

FIG. 8 is a plan view showing a configuration of a scanning signal linearranged in a pixel part of a display device according to an embodimentof the present invention;

FIG. 9 is a plan view showing a configuration of a data signal linearranged in a pixel part of a display device according to an embodimentof the present invention;

FIG. 10 is a plan view showing a configuration of a connection electrodearranged in a pixel part of a display device according to an embodimentof the present invention;

FIG. 11 is a plan view showing a configuration of a pixel electrodearranged in a pixel part of a display device according to an embodimentof the present invention;

FIG. 12 is a plan view showing a configuration of a common auxiliaryelectrode arranged in a pixel part of a display device according to anembodiment of the present invention;

FIG. 13 is a plan view showing a configuration of a common electrodearranged in a pixel part of a display device according to an embodimentof the present invention; and

FIG. 14 is a diagram showing a configuration of a display deviceaccording to an embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the drawings and the like. The present invention may becarried out in various forms without departing from the gist thereof,and is not to be construed as being limited to any of the followingembodiments. Although the drawings may schematically represent thewidth, thickness, shape, and the like of each part in comparison withthe actual embodiment in order to clarify the description, they aremerely examples and do not limit the interpretation of the presentinvention. In the present specification and each of the figures,elements similar to those described previously with respect to thefigures already mentioned are designated by the same reference numerals(or numbers followed by a, b, etc.), and a detailed description thereofmay be omitted as appropriate. Furthermore, the characters “first” and“second” appended to each element are convenient signs used todistinguish each element, and have no further meaning unlessspecifically described.

As used herein, where a member or region is “on” (or “below”) anothermember or region, this includes cases where it is not only directly on(or just under) the other member or region but also above (or below) theother member or region, unless otherwise specified. That is, it includesthe case where another component is included in between above (or below)other members or regions.

In each embodiment of the present invention, when a first conductivelayer, a first insulating layer, and a semiconductor layer are laminatedin this order on a substrate, the direction from the first conductivelayer to the semiconductor layer is referred to as upper or above. Onthe contrary, a direction from the oxide semiconductor layer to thefirst is referred to as lower or below. As described above, forconvenience of explanation, although the term above or below is used,for example, even in the case where the first conductive layer, thefirst insulating layer, and the semiconductor layer are laminated inthis order on the lower side of the substrate as shown in the drawing,the direction from the first conductive layer to the semiconductor layeris also referred to as an upper or above direction. In the followingdescription, for example, the expression “semiconductor layer on thesubstrate” only describes the vertical relationship between thesubstrate and the semiconductor layer as described above, and otherlayers such as the first conductive layer and the first insulating layermay be disposed between the substrate and the semiconductor layer. Aboveor below means the stacking order in the structure in which a pluralityof layers is stacked, and in the case of describing the pixel electrodeabove the transistor, the transistor and the pixel electrode may have apositional relationship in which the transistor and the pixel electrodedo not overlap each other in a plan view unless otherwise specificallylimited. On the other hand, when it is expressed as a pixel electrodevertically above the transistor, it means a positional relationship inwhich the transistor and the pixel electrode overlap in a plan view.

The display panel usually corresponds to a color display, and one pixelincludes a first sub-pixel corresponding to red, a second sub-pixelcorresponding to green, and a third sub-pixel corresponding to blue. Theaperture ratio of each sub-pixel is not necessarily the same, and theaperture ratio is adjusted in consideration of color balance. Theaperture ratio is adjusted by changing the pattern of the lightshielding film (also called a black matrix) on the side of the countersubstrate where the color filter is formed. The light shielding film onthe counter substrate is usually formed of a resin material containing ablack pigment.

It is necessary to reduce the size of the pattern of the light shieldingfilm when forming a high definition pixel. However, it is considereddifficult to perform fine processing of the light shielding film formedof the resin material. Although the light shielding film has alattice-like pattern according to the arrangement of the sub-pixels,forming corner parts with a sharp angle is not easy, so the corner partsmay have a dully curved shape, and the actual aperture may be reducedmore than the design.

Further, the aperture ratio may be affected by an alignment error inbonding the counter substrate including the light shielding film and thearray substrate including the pixel array. These problems may cause theaperture ratio of each sub-pixel to vary widely, which may lead touneven color balance for each panel.

As will be described in detail below, in a display device according toan embodiment of the present invention, the aperture ratio may beprecisely controlled even when forming high definition pixels.

1. Configuration of Display Device (First Substrate)

FIG. 1 is a cross-sectional view showing an outline of each layerarranged on a first substrate SUB1 constituting a display device 100according to an embodiment of the present invention. As shown in FIG. 1, the first substrate SUB1 is arranged with a first transistor Tr1, asecond transistor Tr2, a data signal line DL, a first wiring W1, asecond wiring W2, a connection electrode ZTCO, a pixel electrode PTCO, acommon auxiliary electrode CMTL, and a common electrode CTCO. Althoughthe symbol TCO has no particular meaning, it may be used herein to referto a transparent conductive oxide such as ITO, ZnO, IZO, or the like.The first transistor Tr1 is an element included in the pixel PX of thedisplay device 100, and the second transistor Tr2 is an element includedin the driver circuit. Although the details will be described later, thedriver circuit is a circuit for driving the pixel PX.

1.1 First Transistor

The first transistor Tr1 includes a semiconductor layer OS, a gateinsulating layer G11, and a gate electrode GL1. The semiconductor layerOS is, for example, an oxide semiconductor layer. The semiconductorlayer OS may be a polycrystalline silicon layer. The gate electrode GL1faces the semiconductor layer OS. The gate insulating layer Gl1 isarranged between the semiconductor layer OS and the gate electrode GL1.Although FIG. 1 shows an example of a top gate transistor in which thesemiconductor layer OS is arranged on the substrate SUB side of the gateelectrode GL1, a bottom gate transistor in which the positionalrelationship between the gate electrode GL1 and the semiconductor layerOS is reversed may be used.

The semiconductor layer OS includes a first semiconductor region OS1 anda second semiconductor region OS2. The first semiconductor region OS1 isa region where the semiconductor layer OS overlaps the gate electrodeGL1, and corresponds to a region called a channel in the firsttransistor Tr1. A conductive state and a non-conductive state of thefirst transistor Tr1 are controlled according to a gate voltage appliedto the gate electrode GL1. The second semiconductor region OS2corresponds to a source region and a drain region. The secondsemiconductor region OS2 is continuous from the first semiconductorregion OS1, and is also a region having electrical conductivity higherthan that of the first semiconductor region OS1.

A second insulating layer IL2 is arranged on the gate electrode GL1. Thedata signal line DL is arranged on the second insulating layer IL2. Thedata signal line DL is connected to the second semiconductor region OS2via an opening WCON arranged in the second insulating layer IL2 and thegate insulating layer G11. The data signal line DL is a wire fortransmitting a data signal related to the gradation of an image. A thirdinsulating layer IL3 is arranged on the second insulating layer IL2 andthe data signal line DL. The connection electrode ZTCO is arranged onthe third insulating layer IL3. The connection electrode ZTCO isconnected to the second semiconductor region OS2 via an opening ZCONarranged in the third insulating layer IL3, the second insulating layerIL2, and the gate insulating layer GI1. The connection electrode ZTCO isin contact with the second semiconductor region OS2 at the bottom of theopening ZCON. The connection electrode ZTCO is formed of a transparentconductive film.

A region where the connection electrode ZTCO and the secondsemiconductor region OS2 contact each other is referred to as a firstcontact region CON1. The connection electrode ZTCO is connected to thesecond semiconductor region OS2 in the first contact region CON1arranged at a position which does not overlap the gate electrode GL1 andthe data signal line DL in a plan view.

A fourth insulating layer IL4 is arranged on the connection electrodeZTCO. The fourth insulating layer IL4 is an insulating layer, alsocalled a planarizing layer, and relaxes unevenness formed by thesemiconductor layer OS, the gate electrode GL1, and the like arrangedbelow the fourth insulating layer IL4. The pixel electrode PTCO isarranged on the fourth insulating layer IL4. The pixel electrode PTCO isconnected to the connection electrode ZTCO via an opening PCON arrangedin the fourth insulating layer IL4. A region where the connectionelectrode ZTCO and the pixel electrode PTCO contact each other isreferred to as a second contact region CON2. The second contact regionCON2 overlaps the gate electrode GL1 in a plan view. The pixel electrodePTCO is formed of a transparent conductive film.

A fifth insulating layer IL5 is arranged on the pixel electrode PTCO.The common auxiliary electrode CMTL and the common electrode CTCO arearranged on the fifth insulating layer IL5. The common auxiliaryelectrode CMTL and the common electrode CTCO have different planarpatterns. The common auxiliary electrode CMTL is a metal layer. Thecommon electrode CTCO is a transparent conductive layer. The electricalresistance of the common auxiliary electrode CMTL is lower than that ofthe common electrode CTCO. The common auxiliary electrode CMTL alsofunctions as a light shielding layer, and for example, it is possible tosuppress the occurrence of color mixing by shielding light from adjacentpixels. A plurality of first spacers SP1 are arranged on the commonelectrode CTCO.

The plurality of first spacers SP1 are arranged with a certain distancetherebetween on the first substrate SUB1. The plurality of first spacersSP1 are not arranged corresponding to all the pixels, but are arrangedin an area between a part of the pixels and pixels adjacent thereto. Aheight of each of the plurality of first spacers SP1 is half of a cellgap. A plurality of second spacers is also arranged on the secondsubstrate SUB2. The plurality of second spacers of the second substrateSUB2 and the plurality of first spacers SP1 of the first substrate SUB1are arranged to overlap each other in a plan view.

A first light shielding layer LS1 is arranged on the first substrateSUB1. The first light shielding layer LS1 is arranged in the region ofthe pixel PX. FIG. 1 shows the first light shielding layers LS1 a, LS1 bas the first light shielding layer LS1. The first light shielding layerLS1 may be composed of only the first light shielding layer LS1 a oronly the first light shielding layer LS1 b. The first light shieldinglayer LS1 is arranged in a region where at least the gate electrode GL1and the semiconductor layer OS overlap each other in a plan view. Inother words, the first light shielding layer LS1 is arranged in a regionoverlapping the semiconductor layer OS in a plan view. The first lightshielding layer LS1 prevents light incident from the side of the firstsubstrate SUB1 from reaching the first semiconductor region OS1. Thefirst light shielding layer LS1 defines an aperture range of the pixelPX. A voltage may be applied to the first light shielding layer LS1 whenthe first light shielding layer LS1 is formed of a conductive film. Thefirst light shielding layer LS1 and the gate electrode GL1 may beelectrically connected when a voltage is applied to the first lightshielding layer LS1. The first contact region CON1 is arranged in aregion which does not overlap the first light shielding layer LS1 in aplan view.

1-2. Second Transistor

The driver circuit includes the second transistors Tr2 (p-channeltransistor Tr2-1 and n-channel transistor Tr2-2). Each of the p-channeltransistor Tr2-1 and the n-channel transistor Tr2-2 includes a gateelectrode GL2, a gate insulating layer G12, and a semiconductor layer S.The semiconductor layer S includes a first semiconductor region S1, asecond semiconductor region S2, and a third semiconductor region S3. Thefirst semiconductor region S1 of the semiconductor layer S correspondsto a region for forming a channel, the second semiconductor region S2corresponds to a region for forming a source region and a drain region,and the third semiconductor region S3 corresponds to a region forforming a lightly doped drain (LDD). The gate electrode GL2 includes aregion overlapping the first semiconductor region S1. The gateinsulating layer G12 is arranged between the semiconductor layer S andthe gate electrode GL2. FIG. 1 shows a bottom gate transistor in whichthe gate electrode GL2 is arranged on the first substrate SUB1 side ofthe semiconductor layer S in the second transistors Tr2 (p-channeltransistor Tr2-1 and n-channel transistor Tr2-2). The second transistorsTr2 (p-channel transistor Tr2-1 and n-channel transistor Tr2-2),however, may be a top-gate transistor in which the positionalrelationship between the semiconductor layer S and the gate electrodeGL2 is reversed.

The p-channel transistor Tr2-1 includes the first semiconductor regionS1 and the second semiconductor region S2. The n-channel transistorTr2-2 includes the first semiconductor region S1, the secondsemiconductor region S2, and the third semiconductor region S3. Thefirst semiconductor region S1 overlaps the gate electrode GL2 in a planview, and functions as a channel of the p-channel transistor Tr2-1 andthe n-channel transistor Tr2-2, and the second semiconductor region S2functions as a source region and a drain region. The third semiconductorregion S3 of the n-channel transistor Tr2-2 has a higher resistance thanthat of the second semiconductor region S2 and is also called a lightlydoped drain (LDD), and has a function of preventing hot carrierdegradation.

The first insulating layer 11_1 and the gate insulating layer GI1 arearranged on the semiconductor layer S. The gate insulating layer GI1functions as an interlayer film for the p-channel transistor Tr2-1 andthe n-channel transistor Tr2-2. The second wiring W2 is arranged onthese insulating layers. The second wiring W2 is connected to the secondsemiconductor region S2 via openings arranged in the first insulatinglayer 11_1 and the gate insulating layer GI1. The second insulatinglayer IL2 is arranged on the second wiring W2. The first wiring W1 isarranged on the second insulating layer IL2. The first wiring W1 isconnected to the second wiring W2 through an opening arranged in thesecond insulating layer IL2.

The gate electrode GL2 and the first light shielding layer LS1 a are thesame layer. The second wiring W2 and the gate electrode GL1 are the samelayer. Here, the same layer means that a plurality of members issimultaneously formed by patterning one layer (formed by the sameetching process).

2. Partial Cross-Sectional Structure of the Pixel

FIG. 2 shows an example of a partial cross-sectional structure of thepixel PX. The pixel PX includes the first substrate SUB1, the secondsubstrate SUB2, and the liquid crystal layer LC between the firstsubstrate SUB1 and the second substrate SUB2. As described withreference to FIG. 1 , the first substrate SUB1 includes the first lightshielding layer LS1, the first transistor Tr1, the connection electrodeZTCO, the pixel electrode PTCO, and the common electrode CTCO. Thesecond substrate SUB2 includes the second light shielding layer BM, acolor filter layer CF (first color filter layer CF1, second color filterlayer CF2), and an overcoat layer OC. As described above, the secondsubstrate SUB2 is arranged with the second spacers SP2 at the positioncorresponding to the first spacers SP1. The distance (cell gap) betweenthe first substrate SUB1 and the second substrate SUB2 is held at afixed distance by the first spacers SP1 and the second spacers SP2. Itshould be noted that, in addition to the above configuration, aconfiguration in which the first spacers SP1 directly contacts a layer(for example, an orientation film) forming the outermost surface of thesecond substrate SUB2 can also be adopted, and a configuration in whichthe second spacers SP2 directly contacts a layer forming the outermostsurface of the first substrate SUB1 can also be adopted. Even in such acase, the second contact region CON2 is filled with the material formingthe first spacers SP1, and the second contact region CON2 is planarized.

As shown in FIG. 2 , a configuration lower than the liquid crystal layerLC, that is, the first substrate SUB1 and each configuration laminatedon the first substrate SUB1 may be referred to as an array substrate.Similarly, the structure of the layer above the liquid crystal layer LC,that is, the second substrate SUB2 and the structures laminated on thesecond substrate SUB2 may be referred to as a counter substrate.

The second light shielding layer BM is formed of an organic resinmaterial containing, for example, a black pigment. The second lightshielding layer BM is arranged in the boundary region of the pixel PX.The second light shielding layer BM is arranged in a boundary regionbetween the first color filter layer CF1 and the second color filterlayer CF2. The first color filter layer CF1 and the second color filterlayer CF2 are colored in a predetermined color and have translucency,and are colored in different hues. The overcoat layer OC is arranged onthe color filter layer CF. The liquid crystal layer LC is arrangedbetween the first substrate SUB1 (array substrate) and the secondsubstrate SUB2 (counter substrate). In other words, the liquid crystallayer LC is arranged between the first light shielding layer LS1 and thesecond light shielding layer BM. Note that FIG. 2 shows an alignmentfilm for defining an initial alignment state of the liquid crystal layerLC, which is omitted.

3. Planar Layout of Pixels

The display device 100 has a pixel part 102 in which the plurality ofpixels PX including the elements shown in FIG. 2 are arranged. FIG. 3shows a planar schematic structure of the pixel part 102 when viewedfrom the second substrate SUB2 side. FIG. 3 shows an embodiment in whichthe pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2,and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is asub-pixel corresponding to blue color, the second sub-pixel SPX2 is asub-pixel corresponding to green color, and the third sub-pixel SPX3 isa sub-pixel corresponding to red color. Colors in sub-pixels can bechanged, for example, the first sub-pixel SPX1 may have red and thethird sub-pixel SPX3 may have blue.

FIG. 3 shows that the first sub-pixel SPX1, the second sub-pixel SPX2,and the third sub-pixel SPX3 are arranged in the first direction D1. Thepixels PX including the sub-pixels having the same configuration as thefirst sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixelPX3 are arranged in a first direction D1 and a second direction D2intersecting the first direction D1.

The first sub-pixel SPX1 includes a first semiconductor layer OSa, afirst connection electrode ZTCO1, and a first pixel electrode PTCO1, thesecond sub-pixel SPX2 includes a second semiconductor layer OSb, asecond connection electrode ZTCO2, and a second pixel electrode PTCO2,and the third sub-pixel SPX3 includes a third semiconductor layer OSc, athird connection electrode ZTCO3, and a third pixel electrode PTCO3. Thefirst pixel electrode PTCO1, the second pixel electrode PTCO2, and thethird pixel electrode PTCO3 are surrounded by the first light shieldinglayers LS1, LS2, and the second light shielding layer BM in a plan view,respectively, and a region (a region surrounded by the light shieldinglayer) exposed from these light shielding layers in a plan view becomesa light transmitting region. The first sub-pixel SPX1, the secondsub-pixel SPX2, and the third sub-pixel SPX3 are defined with apertures(translucent regions) by the first light shielding layers LS1, LS2 andthe second light shielding layer BM.

The scanning signal lines SCL extending in the first direction D1 andthe data signal lines DL (the first data signal line DL1, the seconddata signal line DL2, and the third data signal line DL3) extending inthe second direction D2 are arranged in the pixel part 102. One of thescanning signal lines SCL is arranged to intersect with the firstsemiconductor layer OSa, the second semiconductor layer OSb, and thethird semiconductor layer OSc, and the intersecting part functions as agate electrode (GL1). The scanning signal lines SCL and the data signallines DL (first data signal line DL1, second data signal line DL2, andthird data signal line DL3) shown in FIG. 3 are arranged between thefirst light shielding layer LS1 and the second light shielding layer BMin cross sectional views, as is apparent when compared with FIG. 2 .

The first light shielding layer LS1 has a pattern extending in the firstdirection D1. The first light shielding layer LS1 is arranged at aposition overlapping the scanning signal lines SCL extending in thefirst direction D1. A width of the scanning signal line SCL is smallerthan a width of the first light shielding layer LS1. The scanning signallines SCL is arranged in a region inside the pattern of the first lightshielding layer LS1. The light shielding layer LS1 is arranged tointersect with the first semiconductor layer OSa, the secondsemiconductor layer OSb, and the third semiconductor layer OSc. Thefirst light shielding layers LS1, LS2 may have a two-layer structurethat may include the first light shielding layer LS1 a as a lower layerand the first light shielding layer LS1 b as a upper layer. A width ofthe first light shielding layer LS1 b is wider than a width of the firstlight shielding layer LS1 a. The first light shielding layer LS1 a andthe second light shielding layer LS1 b are each formed of a metal film,and a width of the upper first light shielding layer LSb is larger thana width of the first light shielding layer LSa. In other words, it ispreferable that the first light shielding layer LS1 has a structure inwhich at least two metal films are laminated, and the width of the uppermetal layer is larger than the width of the lower metal layer. Both endparts defining the width of the first light shielding layer LS1 overlapwith the first pixel electrodes PTCO1, the second pixel electrodesPTCO2, and the third pixel electrodes PTCO3 arranged along the firstdirection D1. The first light shielding layer LS2 adjacent to the firstlight shielding layer LS1 has the same pattern of the first lightshielding layer LS1 (FIG. 3 shows a part thereof) and is arranged sothat an end part in the width direction overlaps the first pixelelectrodes PTCO1, the second pixel electrodes PTCO2, and the third pixelelectrodes PTCO3. In other words, the first pixel electrodes PTCO1, thesecond pixel electrodes PTCO2, and the third pixel electrodes PTCO3 arearranged so that both ends along the first direction D1 overlap thefirst light shielding layers LS1, LS2.

The second light shielding layer BM includes a pattern extending in thesecond direction D2. The second light shielding layer BM has a shapeoverlapping the first data signal line DL1, the second data signal lineDL2, and the third data signal line DL3 extending in the seconddirection D2 in a plan view. The second light shielding layer BM isarranged so that parts along the second direction D2 overlaps one end ofthe first semiconductor layer OSa, the second semiconductor layer OSb,and the third semiconductor layer OSc. Further, the second lightshielding layer BM may include a pattern extending in the firstdirection D1 and overlapping the scanning signal lines SCL. The patternextending in the first direction D1 is a continuous pattern with thepattern extending in the second direction D2, and is connected to thepatterns extending in the adjacent second direction D2. Part of thesecond light shielding layer BM extending in the first direction D1(pattern extending in the first direction D1) overlaps the scanningsignal lines SCL and the first light shielding layers LS1, LS2, and hasa width narrower than the first light shielding layers LS1, LS2. Thesecond light shielding layer BM is arranged to overlap both sides alongthe second direction D2 of the first pixel electrodes PTCO1, the secondpixel electrodes PTCO2, and the third pixel electrodes PTCO3.

As described above, the first pixel electrodes PTCO1, the second pixelelectrodes PTCO2, and the third pixel electrodes PTCO3 are surroundedwhile partially overlapping the first light shielding layers LS1, LS2,and the second light shielding layer BM in a plan view. Here, an area ofa region where the first light shielding layers LS1, LS2 overlap one ofthe first pixel electrodes PTCO1 is different from an area of a regionwhere the first light shielding layers LS1, LS2 overlap one of thesecond pixel electrodes PTCO2 and one of the third pixel electrodesPTCO3. Specifically, the area where the first light shielding layersLS1, LS2 overlap the one of first pixel electrodes PTCO1 is larger thanthe area where the first light shielding layers LS1, LS2 overlap one ofthe second pixel electrodes PTCO2 and one of the third pixel electrodesPTCO3. The area where the first light shielding layers LS1, LS2 overlapone of the second pixel electrodes PTCO2 is smaller than the area wherethe first light shielding layers LS1, LS2 overlap one of the first pixelelectrodes PTCO1 and larger than the area where the first lightshielding layers LS1, LS2 overlap one of the third pixel electrodesPTCO3. The area where the first light shielding layers LS1, LS2 overlapone of the third pixel electrodes PTCO3 is smaller than the area wherethe first light shielding layers LS1, LS2 overlap one of the first pixelelectrodes PTCO1 and one of the second pixel electrodes PTCO2.

FIG. 4 is an enlarged view of the first sub-pixel SPX1, the secondsub-pixel SPX2, and the third sub-pixel SPX3. The first pixel electrodePTCO1, the second pixel electrode PTCO2, and the third pixel electrodePTCO3 partially overlapped and surrounded by the first light shieldinglayers LS1, LS2, and the second light shielding layer BM in a plan view.The first sub-pixel SPX1 has a first aperture OP1 exposed from the firstlight shielding layers LS1, LS2, the second sub-pixel SPX2 has a secondaperture OP2, and the third sub-pixel SPX3 has a third aperture OP3.

The sizes (areas) of the first aperture OP1, the second aperture OP2,and the third aperture OP3 are different because the widths of the firstlight shielding layers LS1, LS2 are different for each aperture. Thatis, while the width X1 of the first sub-pixel SPX1, the second sub-pixelSPX2, and the third sub-pixel SPX3 in the first direction D1 is the samefor the three pixels, the width in the second direction D2 has therelationship Y1<Y2<Y3 when the first sub-pixel SPX1 has the length Y1,the second sub-pixel SPX2 has the length Y2, and the third sub-pixelSPX3 has the length Y3. The difference in the length in the seconddirection D2 in each sub-pixel is based on the difference in the widths(or the length in the second direction D2) of the first light shieldinglayers LS1, LS2. The first light shielding layers LS1, LS2 have a partcorresponding to the first sub-pixel SPX1 having a large width, a partcorresponding to the third sub-pixel SPX3 having a small width, and apart corresponding to the second sub-pixel SPX2 having an intermediatewidth.

In this way, the width of one or both of the first light shieldinglayers LS1, LS2 sandwiching the first sub-pixel SPX1, the secondsub-pixel SPX2, and the third sub-pixel SPX3 varies along the firstdirection D1, so that the area of the aperture of each pixel can be madedifferent. That is, it is possible to make the aperture ratios of thefirst sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixelSPX3 different by adjusting the widths of the first light shieldinglayer LS1 and the first light shielding layer LS2. Although thisembodiment shows an example in which the widths of the first lightshielding layers LS1, LS2 are different, the widths of the second lightshielding layer BM may also be different at the same time. The apertureratio refers to the ratio of the area not shielded by the lightshielding layer to the area occupied by one pixel (or sub-pixel). Thearea of each pixel PX (or sub-pixel SPX) is determined, for example,according to the distance between the centers of adjacent scanningsignal lines SCL and adjacent data signal lines DL, and has a sizecommon to each sub-pixel regardless of color.

When the first sub-pixel SPX1 is a pixel corresponding to blue, thesecond sub-pixel SPX2 is a sub-pixel corresponding to green, and thethird sub-pixel SPX3 is a sub-pixel corresponding to red, it is possibleto increase the aperture ratio (or the area of the aperture) of thesub-pixel corresponding to red by the first light shielding layer LS1 incomparison with the aperture ratio (or the area of the aperture) of thesub-pixel corresponding to blue and the sub-pixel corresponding togreen.

The pattern width of the first light shielding layers LS1, LS2 variesalong the first direction D1 in order to make the size of theoverlapping areas with each of the pixel electrodes arranged in thefirst direction D1 different.

The first light shielding layer LS1 is also utilized to shield theregion of the spacer SP. FIG. 5 shows the pattern of the first lightshielding layer LS1 in the region of the first spacer SP1. Although thefirst light shielding layer LS1 has a pattern the width of which changesat a certain manner along the first direction D1, it also has anirregular pattern in the region of the first spacer SP1. That is, thefirst light shielding layer LS1 has a pattern wider than other regionsin order to shield the region of the first spacer SP1.

On the other hand, the second light shielding layer BM does not have anirregular pattern similar to the first light shielding layer SL1 even inthe region where the first spacer SP1 is arranged, but has the samepattern as the other regions. Although a part of the first spacer SP1 isexposed from the second light shielding layer BM, since the first lightshielding layer LS1 shields the first spacer SP1 from light, there is noinfluence on the display of the image. Since the second light shieldinglayer BM is formed of a resin material, it is difficult to form a fineand precise pattern. In order to shade the first spacer SP1 with thesecond shading layer BM, it is necessary to design a wide area of theshading part in consideration of the margin. On the other hand,according to the present embodiment, since the first light shieldinglayer LS1 has a fine pattern, the first spacer SP1 can be reliablyshielded from light, and the aperture ratio of the pixel can beprevented from becoming smaller more than necessary. Therefore,according to the present embodiment, as shown in FIG. 5 , a part of thefirst spacer SP1 is not shielded by the second light shielding layer BMwhen the relationship between the second light shielding layer BM andthe first spacer SP1 is viewed. That is, the first spacer SP1 (or thewhole of the spacer, which is formed by the first spacer SP1 and thesecond spacer SP2 in the present embodiment) has a lower bottom surfaceon the first substrate SUB1 side overlapping the entire first lightshielding layer LS1 arranged on the first substrate SUB1, while an upperbottom surface on the second substrate SUB2 side is partially exposedfrom the second light shielding layer BM arranged on the secondsubstrate SUB2. As shown in FIG. 5 , the first spacer SP1 is not onlyarranged on the second contact region CON2 of a predetermined pixel, butalso overlaps the pixel electrode PTCO over the second contact regionCON2, the semiconductor layer OS connected to the pixel electrode PTCO,and the pixel electrode adjacent to the pixel electrode PTCO in thesecond direction D2. As described above, when a high definition pixelpart 102 is formed, the spacer becomes relatively larger than the sizeof the pixel PX. In this embodiment, the radius of the first spacer SP1is larger than the length in the first direction of the pixel PX definedbetween the centers of the data signal lines DL, and the first spacerSP1 overlaps any of the pair of adjacent data signal lines DL2, DL3.

A region where the first pixel electrode PTCO1 is exposed from the firstlight shielding layers LS1, LS2 and the second light shielding layer BMconstitutes a light transmissive region. This light transmissive regioncorresponds to the aperture of the first sub-pixel SPX1. That is, theaperture ratio of the first sub-pixel SPX1 is defined by the first lightshielding layers LS1, LS2 and the second light shielding layer BM.Similarly, the aperture ratios of the second sub-pixel SPX2 and thethird sub-pixel SPX3 are also defined by the first light shieldinglayers LS1, LS2 and the second light shielding layer BM. The apertureratios of the first sub-pixel SPX1, the second sub-pixel SPX2, and thethird sub-pixel SPX3 are different. The difference in the aperture ratioof each pixel is defined by the difference in the area where the firstlight shielding layers LS1, LS2 overlap the pixel electrode.

It should be noted that the first light shielding layers LS1, LS2 arearranged on the first substrate SUB1, and the second light shieldinglayer BM is arranged on the second substrate SUB2. As shown in FIG. 1and FIG. 2 , the first light shielding layer LS1 is arranged on a lowerlayer side than the scanning signal line SCL (and the gate electrodeGL1) and the pixel electrode PTCO. The first light shielding layer LS1is formed with a metal film on the first substrate SUB1, and theabove-described pattern is formed by a photolithography process. Thefirst light shielding layer LS1 is a layer first patterned on the firstsubstrate SUB1, and the scanning signal line SCL (and the gate electrodeGL1) and the pixel electrode PTCO formed in the subsequent steps arepositioned by alignment markers formed in the same layer as the firstlight shielding layer LS1. The first light shielding layer LS1 is formedby dry etching or wet etching a metal film which is an inorganicmaterial, so that the first light shielding layer LS1 can be formed in afine pattern. The pixel electrode PTCO has a transparent conductive filmformed on the first substrate SUB1 formed in a predetermined shapethrough a photolithography process. The mutual positions of the firstlight shielding layer LS1 and the pixel electrode PTCO depend on thealignment accuracy of the photomask in the exposure apparatus and can bealigned with high accuracy. On the other hand, the second lightshielding layer BM is formed of an organic resin material containing ablack pigment. Although the second light shielding layer BM is notsuitable for forming a high-definition pattern such as the first lightshielding layer LS1, the second light shielding layer BM can beinexpensively manufactured in a region having a large area with a smallnumber of steps.

If the aperture ratio of pixels is to be adjusted only with the secondlight shielding layer BM formed on the second substrate SUB2, a marginmust be maintained to account for alignment accuracy (misalignment oflamination) when the first substrate SUB1 and second substrate SUM2 arebonded together. The display device 100 according to the presentembodiment finely controls the aperture ratio of pixels by combining theabove two kinds of light shielding layers. That is, not only the secondlight shielding layer BM arranged on the second substrate SUB2 definesthe aperture ratio of the pixels, but also the first light shieldinglayer LS1 arranged on the first substrate SUB1 and the second lightshielding layer BM arranged on the second substrate SUB2 are utilized,and the aperture area (at least with respect to the definition in thesecond direction) is controlled by the first light shielding layer LS1to precisely control the aperture ratio of each pixel. Thus, even if thepixel is formed to a high definition (even if the size of the pixel isnarrowed), the aperture ratio of the pixel can be precisely controlled.

4. Detailed Layout of Each Layer Constituting the Pixel

A detailed layout of each layer constituting the pixel PX will bedescribed below.

4-1. First Light Shielding Layer

FIG. 6 shows the first light shielding layers LS1, LS2, LS3. The firstlight shielding layers LS1, LS2, LS3 have a pattern extending in thefirst direction D1. As described with reference to FIG. 3 , the patternwidth of the first light shielding layer LS1 is different according tothe arrangement of the pixels. That is, the first light shielding layerLS1 includes a part having a wider width along the first direction D1and a part having a narrower width than the part having a wider width.For example, when the first sub-pixel SPX1, the second sub-pixel SPX2,and the third sub-pixel SPX3 as shown in FIG. 3 are arrangedperiodically along the first direction D1, the first light shieldinglayer LS1 has a pattern that changes periodically. The same is true forthe first light shielding layers LS2, LS3.

As shown in FIG. 1 , the first light shielding layer LS1 may have atwo-layer structure comprised of the first light shielding layer LS1 aand the first light shielding layer LS1 b. It is possible to enhance thelight shielding performance by forming the first light shielding layerLS1 into a metal film with a two-layer structure.

4-2. Semiconductor Layer

As shown in FIG. 7 , the first semiconductor layer OSa, the secondsemiconductor layer OSb, and the third semiconductor layer OSc haveisland patterns extending in the second direction D2. The firstsemiconductor layer OSa, the second semiconductor layer OSb, and thethird semiconductor layer OSc are arranged on the upper layer side ofthe first light shielding layer LS1. The first semiconductor layer OSa,the second semiconductor layer OSb, and the third semiconductor layerOSc are arranged so that they partially overlap the first lightshielding layer LS1.

4-3. Scanning Signal Line

FIG. 8 shows the scanning signal line SCL. The scanning signal line SCLextends in the first direction D1 to intersect with the firstsemiconductor layer OSa, the second semiconductor layer OSb, and thethird semiconductor layer OSc. A part where the scanning signal line SCLintersects the first semiconductor layer OSa, the second semiconductorlayer OSb, and the third semiconductor layer OSc functions as a gateelectrode (GL1). The pattern of the scanning signal line SCL (gateelectrode GL1) is arranged inside the pattern of the first lightshielding layer LS1.

4-4. Data Signal Line

FIG. 9 shows the first data signal line DL1, the second data signal lineDL2, and the third data signal line DL3. The first data signal line DL1,the second data signal line DL2, and the third data signal line DL3extend in the second direction D2 and are arranged to intersect thescanning signal line SCL. As shown in FIG. 9 , the aperture WCON isarranged in a region overlapping the first data signal line DL1, thesecond data signal line DL2, and the third data signal line DL3 near oneend of the island pattern of the first semiconductor layer OSa, thesecond semiconductor layer OSb, and the third semiconductor layer OSc. Amain part of the first semiconductor layer OSa is arranged between thefirst data signal line DL1 and the second data signal line DL2 andextends in the second direction D2. One end of the first semiconductorlayer OSa has a pattern bent toward the opening WCON from a partsandwiched between the first data signal line DL1 and the second datasignal line DL2. The first data signal line DL1 is arranged to overlapthe opening WCON. The first semiconductor layer OSa is connected to thefirst data signal line DL1 at the opening WCON. The same is true for thesecond semiconductor layer OSb and the third semiconductor layer OSc.

4-5. Connection Electrode

As shown in FIG. 10 , the opening ZCON is arranged to overlap the islandpattern of the first semiconductor layer OSa, the second semiconductorlayer OSb, and the third semiconductor layer OSc. While the opening WCONis arranged on one end side of the first semiconductor layer OSa, thesecond semiconductor layer OSb, and the third semiconductor layer OSc,the opening ZCON is arranged on the other end side of the firstsemiconductor layer OSa, the second semiconductor layer OSb, and thethird semiconductor layer OSc. The first light shielding layer LS1 orthe scanning signal line SCL passes between one end and the other end ofthe first semiconductor layer OSa, the second semiconductor layer OSb,and the third semiconductor layer OSc. The opening ZCON is arranged at aposition not overlapping the scanning signal line SCL.

The connection electrode ZTCO is arranged between the first data signalline DL1 and the second data signal line DL2 to overlap the firstsemiconductor layer OSa. The connection electrode ZTCO is connected tothe first semiconductor layer OSa at the opening ZCON (first contactregion CON1). The second semiconductor layer OSb and the thirdsemiconductor layer OSc are similarly connected to the connectionelectrode ZTCO. The connection electrode ZTCO has a pattern extendingalong the second direction D2 and is arranged to extend from a partwhere the opening ZCON is formed to a region exceeding the scanningsignal line SCL.

4-6. Pixel Electrode

FIG. 11 shows the first pixel electrode PTCO1, the second pixelelectrode PTCO2, and the third pixel electrode PTCO3. The first pixelelectrode PTCO1 is connected to the first connection electrode ZTCO1through the opening PCON, the second pixel electrode PTCO2 is connectedto the second connection electrode ZTCO2 through the opening PCON, andthe third pixel electrode PTCO3 is connected to the third connectionelectrode ZTCO3 through the opening PCON. The opening PCON is arrangedin a region near the upper ends of the patterns of the first connectionelectrode ZTCO1, the second connection electrode ZTCO2, and the thirdconnection electrode ZTCO3 and overlaps the pattern of the scanningsignal line SCL (gate electrode GL1). The first pixel electrode PTCO1 isarranged between the first data signal line DL1 and the second datasignal line DL2 to overlap the scanning signal line SCL (gate electrodeGL1), the semiconductor layer OS1 a, and the first connection electrodeZTC1 and extend in the second direction D2. The same is true for thesecond pixel electrode PTCO2 and the third pixel electrode PTCO3.

4-7. Common Auxiliary Electrode

FIG. 12 shows a common auxiliary electrode CMTL. The common auxiliaryelectrode CMTL has a lattice-like pattern surrounding the first pixelelectrode PTCO1, the second pixel electrode PTCO2, and the third pixelelectrode PTCO3. The common auxiliary electrode CMTL includes a verticalpattern extending in the second direction D2 to overlap the first datasignal line DL1, the second data signal line DL2, and the third datasignal line DL3, and a horizontal pattern extending in the firstdirection D1 to overlap part of the opening PCON. A width of the patternextending in the first direction D1 of the common auxiliary electrodeCMTL is narrower than the width of the first light shielding layer LS1.The common auxiliary electrode CMTL is arranged over the entire pixelpart 102. In other words, the common auxiliary electrode CMTL has aplurality of openings that expose the first pixel electrode PTCO1, thesecond pixel electrode PTCO2, and the third pixel electrode PTCO3.

The common auxiliary electrode CMTL is formed of a metal film. Thecommon auxiliary electrode CMTL is utilized as an auxiliary electrodefor reducing the resistance of the common electrode CTCO, which isformed of a transparent conductive film on the common electrode CMTL andextends over substantially the entire surface of the pixel part 102.

According to the above configuration, it is possible to define theaperture widths of the first pixel PX1, the second pixel PX2, and thethird pixel PX3 in the first direction D1 by adjusting the widths of thecommon auxiliary electrodes CMTL. That is, it is possible to form aregion overlapping the first pixel electrode PTCO1, the second pixelelectrode PTCO2, and the third pixel electrode PTCO3 by widening thewidth of the common auxiliary electrode CMTL, and to add a function as alight shielding layer. In other words, the common auxiliary electrodeCMTL can replace the function of the second light shielding layer BMarranged on the second substrate SUB2.

FIG. 3 shows an example in which the aperture of a pixel is defined bythe first light shielding layer LS1 and the second light shielding layerBM, and as shown in FIG. 12 , it is also possible to define the aperturesize (aperture ratio) of the pixel by the first light shielding layerLS1 and the common auxiliary electrode CMTL. More specifically, thecommon auxiliary electrode CMTL is arranged to overlap each data signalline and extend in the second direction, and defines the width of theaperture of each pixel PX in the first direction instead of the secondlight shielding layer BM. Since the common auxiliary electrode CMTL ispatterned by photolithography in the same manner as the first lightshielding layer LS1, the aperture ratio can be precisely defined even ifthe pixel PX is reduced in size. According to such a configuration, thesecond light shielding layer BM on the counter substrate side (secondsubstrate side SUB2) may or may not be arranged. The width of thehorizontal pattern of the common auxiliary wiring CMTL in the seconddirection is equal to the width of the opening PCON, and the width issmaller than the widths of the first light shielding layers LS1, LS2while covering the opening PCON.

4-8. Common Electrode

FIG. 13 shows the common electrode CTCO. The common electrode CTCO iscommonly arranged for a plurality of pixels. The common electrode CTCOis provided with slits SL in a region corresponding to the aperture ofthe first pixel PX1, the second pixel PX2, and the third pixel PX3. Theslit SL has a curved shape (a vertically long S-shape), and has a shapein which the width in the extending direction decreases as the tip ends.As described above, the pixel PX driving the liquid crystal in the IPSmode (In-Plane Switching mode) or FFS mode (Fringe Field Switching mode)is provided.

4-9. Material of Each Member Constituting the Pixel

A rigid substrate having translucency and no flexibility such as a glasssubstrate, a quartz substrate and a sapphire substrate can be used asthe first substrate SUB1 and the second substrate SUB2. On the otherhand, when the first substrate SUB1 and the second substrate SUB2require flexibility, a flexible substrate containing a resin such as apolyimide substrate, an acrylic substrate, a siloxane substrate, or afluor resin substrate can be used as the substrate. In order to improvethe heat resistance of the first substrate SUB1 and the second substrateSUB2, impurities may be introduced into the resin.

A metal can be used as the scanning signal line SCL (gate electrodeGL1), the gate electrode GL2, the data signal line DL, the first wiringW1, the second wiring W2, the first light shielding layer LS1, and thecommon auxiliary electrode CMTL. For example, aluminum (Al), titanium(Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium(Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloysor compounds thereof are used as these members. The material of thesemembers may be used as a single layer or may be used as a laminate.

An insulating material can be used as the gate insulating layers GI1,G12, the first insulating layer IL1, the second insulating layer IL2,the third insulating layer IL3, the fourth insulating layer IL4, and thefifth insulating layer IL5. For example, an inorganic insulatingmaterial such as silicon oxide (SiO_(x)), silicon oxynitride(SiO_(x)N_(y)), silicon nitride (Si_(x)N_(y)), aluminum oxide (AlO_(x)),aluminum oxynitride (AlO_(x)N_(y)), and aluminum nitride (AlN_(x)) canbe used as the first insulating layer IL1, the second insulating layerIL2, the third insulating layer IL3, and the fifth insulating layer IL5.These insulating layers preferably contain few defects. An organicinsulating material such as a polyimide resin, an acrylic resin, anepoxy resin, a silicone resin, a fluor resin, or a siloxane resin can beused as the fourth insulating layer IL4. An organic insulating materialmay be used as the gate insulating layers GI1, GI2, the first insulatinglayer IL1, the second insulating layer IL2, the third insulating layerIL3, and the fifth insulating layer IL5. The material of these membersmay be used as a single layer or may be used as a laminate.

As an example of the insulating layer, SiO_(x) having a thickness of 100nm is used as the gate insulating layer GI1. SiO_(x)/Si_(x)N_(y)/SiO_(x)having a total thickness of 600 nm to 700 nm is used as the firstinsulating layer IL1. SiO_(x)/Si_(x)N_(y) having a total thickness of 60nm to 100 nm is used as the gate insulating layer G12.SiO_(x)/Si_(x)N_(y)/SiO_(x) with a total thickness of 300 nm to 500 nmis used as the second insulating layer IL2. SiO_(x) (single layer),Si_(x)N_(y) (single layer), or their laminations having a totalthickness of 200 nm to 500 nm are used as the third insulating layerIL3. An organic layer having a thickness of 2 μm to 4 μm is used as thefourth insulating layer IL4. Si_(x)N_(y) (single layer) having athickness of 50 nm to 150 nm is used as the fifth insulating layer IL5.

A metal oxide (oxide semiconductor) having semiconductor properties canbe used as the semiconductor layer OS. The semiconductor layer OS hastransparency. For example, oxide semiconductors containing indium (In),gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, anoxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 canbe used. However, the oxide semiconductor containing In, Ga, Zn, and Oused in this embodiment is not limited to the above composition, and anoxide semiconductor having a composition different from the above may beused. For example, the ratio of In may be larger than the above in orderto improve the mobility. In order to increase the band gap and reducethe influence of light irradiation, the ratio of Ga may be made largerthan the above.

The oxide semiconductor containing In, Ga, Zn and O may be doped withother elements. For example, metal elements such as Al and Sn may beadded to the oxide semiconductor. In addition to the oxidesemiconductors described above, oxide semiconductors including In and Ga(IGO), oxide semiconductors including In and Zn (IZO), oxidesemiconductors including In, Sn and Zn (ITZO), and oxide semiconductorsincluding In and W may be used as the semiconductor layer OS. Thesemiconductor layer OS may be amorphous or crystalline. Thesemiconductor layer OS may be a mixed phase of amorphous and crystal.

A transparent conductive layer is used as the connection electrode ZTCO,the pixel electrode PTCO (first pixel electrode PTCO1, second pixelelectrode PTCO2, and third pixel electrode PTCO3), and the commonelectrode CTCO. A mixture of indium oxide and tin oxide (ITO) and amixture of indium oxide and zinc oxide (IZO) can be used as thetransparent conductive layer. Materials other than those described abovemay be used as the transparent conductive layer.

Configuration of the Display Device

FIG. 14 shows a configuration of the display device 100 according to anembodiment of the present invention. The display device 100 includes thefirst substrate SUB1, the second substrate SUB2, the driver IC 110, andthe flexible printed circuit board 112. As shown in this embodiment, thepixel PX including the first light shielding layer LS1 is arranged onthe first substrate SUB1, and the second light shielding layer BM andthe color filter layer CF are arranged on the second substrate SUB2. Asealing material (not shown) is arranged between the first substrateSUB1 and the second substrate SUB2. The first substrate SUB1 and thesecond substrate SUB2 are bonded by a sealing material.

The first substrate SUB1 includes a pixel part 102 in which theplurality of pixels PX are arranged, the scanning signal line drivercircuit 104 arranged in an area outside the pixel part 102, the datasignal line selection circuit 106, and a terminal part 108 forming aconnection with the flexible printed circuit board 112. The driver IC110 is mounted on the flexible printed circuit board 112. The pixel PXincludes the first sub-pixel SPX1, the second sub-pixel SPX2, and thethird sub-pixel SPX3. The scanning signal line SCL is connected to thescanning signal line driver circuit 104, and the first data signal lineDL1, the second data signal line DL2, and the third data signal line DL3are connected to the data signal line selection circuit 106.

The first transistor Tr1 shown in FIG. 1 is arranged in the firstsub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.The second transistor Tr2 is utilized in the scanning signal line drivercircuit 104 and the data signal line selection circuit 106. The pixelpart 102 is constituted by the first sub-pixel SPX1, the secondsub-pixel SPX2, and the third sub-pixel SPX3 shown in FIG. 3 and FIG.

Each of the embodiments described above as an embodiment of the presentinvention can be appropriately combined and implemented as long as theydo not contradict each other. Further, the addition, deletion, or designchange of components as appropriate by those skilled in the art based oneach embodiment are also included in the scope of the present inventionas long as they are provided with the gist of the present invention.

It is understood that, even if the effect is different from thoseprovided by each of the above-described embodiments, the effect obviousfrom the description in the specification or easily predicted by personsordinarily skilled in the art is apparently derived from the presentinvention.

What is claimed is:
 1. A display device, comprising; a first substrate;a pixel with an aperture on the first substrate; a first light shieldinglayer and a second light shielding layer on the first substrate; asecond substrate; and a third light shielding with openings in a closedshape on the second substrate, wherein the first light shielding layerincludes a first part extending in a first direction, the second lightshielding layer includes a second part extending in the first direction,the third light shielding layer includes third parts extending in asecond direction intersecting the first direction, the aperture has afirst edge, a second edge facing the first edge, a third edge, and afourth edge facing the third edge, the first and second edges extends inthe first direction, the third and fourth edges extends in the seconddirection, the first edge is an edge of the first part, the second edgeis an edge of the second part, the third edge is an edge of one of thethird parts, and the fourth edge is an edge of another of the thirdparts.
 2. The display device according to claim 1, further comprising afirst wiring line and a second wiring line that extend in the firstdirection, wherein the first light shielding layer overlaps the firstwiring line, the second light shielding layer overlaps the second wiringline, a width of the first light shielding layer in the second directionis wider than a width of the first wiring line in the second direction,and a width of the second light shielding layer in the second directionis wider than a width of the first wiring line in the second direction.3. The display device according to claim 1, further comprising a wiringline extending in the second direction, wherein the wiring line overlapsthe third light shielding layer, and a width of the third lightshielding layer in the first direction is wider than a width of thewiring line in the first direction.
 4. The display device according toclaim 1, further comprising a second pixel adjacent to the pixel in thefirst direction, wherein the first light shielding layer has a firstportion overlapping the pixel and a second portion overlapping thesecond pixel, the first light shielding layer has a first entire widthand a second entire width in the second direction, the first entirewidth including the first portion, the second entire width including thesecond portion, and the first entire width is different from the secondentire width.
 5. The display device according to claim 1, wherein thefirst and second light shielding layers are a metal film, and the thirdlight shielding layer is a resin film.
 6. The display device accordingto claim 1, wherein both of the first and second light shielding layerinclude an upper metal layer and a lower metal layer, and a width of theupper metal layer is wider than a width of the lower metal layer in thesecond direction.
 7. The display device according to claim 1, whereinthe third light shielding layer includes fourth parts extending in thefirst direction, an edge of a first one of the fourth parts overlaps thefirst light shielding layer, and an edge of a second one of the fourthparts overlaps the second light shielding layer.
 8. The display deviceaccording to claim 1, further comprising a third pixel adjacent to thepixel in the second direction, wherein the third pixel has a thirdaperture with a fifth edge extending in the first direction, and thefifth edge is an opposite edge of the first part, the opposite edgebeing opposite to the edge of the first part.
 9. The display deviceaccording to claim 1, wherein the pixel has a pixel electrode, and thepixel electrode overlaps the first to third light shielding layers. 10.The display device according to claim 9, wherein the pixel has a portionwhich the first to third light shielding layers exposes, and the portioncorresponds to the aperture.
 11. The display device according to claim10, further comprising a second pixel adjacent to the pixel in the firstdirection, wherein the second pixel has a second aperture which thefirst to third light shielding layers exposes, and a size of theaperture is different from a size of the second aperture.
 12. Thedisplay device according to claim 9, wherein the pixel has a portionwhich does not overlap the first to third light shielding layers, andthe portion corresponds to the aperture.
 13. The display deviceaccording to claim 1, wherein the pixel emits light from the aperture toan outside of the pixel.
 14. A display device, comprising; a firstsubstrate; a pixel with an aperture on the first substrate; a firstlight shielding layer and a second light shielding layer on the firstsubstrate; a second substrate; and a third light shielding with anopening in a closed shape on the second substrate, wherein the firstlight shielding layer includes a first part extending in a firstdirection, the second light shielding layer includes a second partextending in the first direction, the opening includes two edgesextending in a second direction intersecting the first direction, theaperture has a first edge, a second edge facing the first edge, a thirdedge, and a fourth edge facing the third edge, the first and secondedges extends in the first direction, the third and fourth edges extendsin the second direction, the first edge corresponds to an edge of thefirst part, the second edge corresponds to an edge of the second part,and the third edge and the fourth edge correspond to the two edges ofthe opening.
 15. The display device according to claim 14, furthercomprising a first wiring line and a second wiring line that extend inthe first direction, wherein the first light shielding layer overlapsthe first wiring line, the second light shielding layer overlaps thesecond wiring line, a width of the first light shielding layer in thesecond direction is wider than a width of the first wiring line in thesecond direction, and a width of the second light shielding layer in thesecond direction is wider than a width of the first wiring line in thesecond direction.
 16. The display device according to claim 14, furthercomprising a wiring line extending in the second direction, wherein thewiring line overlaps the third light shielding layer, and a width of thethird light shielding layer in the first direction is wider than a widthof the wiring line in the first direction.
 17. The display deviceaccording to claim 14, wherein further comprising a second pixeladjacent to the pixel in the first direction, wherein the first lightshielding layer has a first portion overlapping the pixel and a secondportion overlapping the second pixel, the first light shielding layerhas a first entire width and a second entire width in the seconddirection, the first entire width including the first portion, thesecond entire width including the second portion, and the first entirewidth is different from the second entire width.
 18. A display device,comprising; a first substrate; a pixel located on the first substrateand having a region that emits light to an outside of the pixel; a firstlight shielding layer and a second light shielding layer on the firstsubstrate; a second substrate; and a third light shielding on the secondsubstrate, wherein the first light shielding layer includes a first partextending in a first direction, the second light shielding layerincludes a second part extending in the first direction, the third lightshielding includes two edges extending in a second directionintersecting the first direction, and the region is surrounded by thefirst part, the second part, and the two edges.
 19. The display deviceaccording to claim 18, further comprising a second pixel adjacent to thepixel in the first direction, wherein the first light shielding layerhas a first portion overlapping the pixel and a second portionoverlapping the second pixel, the first light shielding layer has afirst entire width and a second entire width in the second direction,the first entire width including the first portion, the second entirewidth including the second portion, and the first entire width isdifferent from the second entire width.
 20. The display device accordingto claim 18, further comprising a second pixel adjacent to the pixel inthe first direction, wherein the second pixel has a second region thatemits light to an outside of the second pixel, and a size of the regionis different from a size of the second region.